The present invention concerns optimal placement of inter-area connectors on the periphery of bounded areas on an integrated circuit
An integrated circuit is generally divided into bounded areas. All the circuitry within each bounded area may be generally referred to as a circuit component. Signal connectors within a circuit component are connected to other signal connectors in the same circuit component through internal connector lines. Signal connectors are connected to signal connectors in other circuit components by first being connected through internal connector lines to inter-area connectors located on the periphery of the circuit components. The inter-area connectors are connected together through inter-area connector lines. A group of all signal connectors and inter-area connectors which are to be routed together is called a connector net. All connector lines, whether internal or inter-area, have a measurable width and take up space on the integrated circuit which is directly proportional to their length.
When selecting locations on the integrated circuit in which to place the circuit components, it is desirable to select locations so that the area on the integrated circuit is optimally utilized. Optimal placement of circuit components occurs when the dead space, that is area between circuit components which is not utilized by circuit components, is minimized, and when the estimated total length of connector lines is minimized.
Once circuit components are placed on an integrated circuit, a router is used to route connector lines between the signal connectors. In the prior art, typically, a router program is used to first route all signal connectors internally within each circuit component. In doing this internal routing, inter-area connectors are first placed on the periphery of each circuit component to account for routing of nets of signal connectors which span more than one circuit component. The process of internal routing may include an internal router going though multiple stages of congestion estimation, initial routing, and rip-up and re-route in order to ensure that the number of tracks required in each internal channel does not exceed the channel capacity. Once the internal routing is complete, an inter-area router connects all the inter-area connectors.
In the prior art, when selecting a location on a periphery of a circuit component for the placement of an inter-area connector, the prime objective has been to align the inter-area connector with other inter-area or internal connectors which belong to the same connector net. However, this often results in non-optimal routing of connector lines within circuit components. There has been little or no work done on the problem of selecting the location of inter-area connectors to simultaneously optimize inter-area and internal routing of connector lines. For examples of prior art routing schemes, see for example, Charles Ng, Sunil Ashtaputre, Elizabeth Chambers, Kieu-huong Do, Siu-tong Hui, Rajiv Mody, and Dale Wong; A Hierarchical Floor-Planning, Placement, and Routing Tool for Sea-of-Gates Designs, IEEE 1989 Custom Integrated Circuits Conference, pp. 3.3.1-3.3.4; and see David Hsu, Leslie Grate, Charles Ng, Mark Hartoog and Denis Bohm, The ChipCompiler, An Automated Standard Cell/Macrocell Physical Design Tool, IEEE 1987 Custom Integrated Circuits Conference, p 488-491.